User:Oyz

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oyz was born in Seoul, Korea,  M.Sc. and Ph.D. degrees in electronic and electrical engineering
from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 1997, 1999 and 2005, respectively.


SungEun Jo
Hangul
조성은
Hanja
趙成殷
Revised RomanizationJo SeongEun
McCune–ReischauerCho SŏngŬn

My area is in mixed-signal processing, which requires broad knowledge over analog signal conditioning and digital signal processing. I am also interested in circuit fabrication on the impedance controlled PCB to achieve the best performance of analog circuits. Speaking of digital processing, I am focusing on RTL implementation on FPGA system in order to obtain low-latency and concurrent responses, which are not easily expected from ordinary microcontroller or DSP based system.

Back in academic path, I was a postdoctoral researcher with the Computer Science Department, Stanford University, Stanford, CA, working for Prof. Gene H. Golub, investigating real-time algorithms relating to total least squares (TLS). His research interests include numerical methods and optimization for systems and control, data analysis based on TLS or errors-in-variables (EIV) modeling, and applications of equality constrained minimization in adaptive algorithms such as the affine projection algorithm and the normalized LMS filtering.

Contribution on wikipedia[edit]

  • What I created

Bidiagonalization, Block matrix pseudoinverse, Simple rational approximation, Secular function, Errors-in-variables model, Block LU decomposition.

  • What I revised

Trace (linear algebra), Least squares, Secular equation, QR decomposition, Matrix inversion lemma.

Curriculum vitae - Sung-Eun Jo[edit]

JOB_OBJECTIVE[edit]

- Leading engineering position in analog-digital mixed signal processing on FPGA-based system: Electronic specification, PCB fabrication, up to algorithm implementation.
- Research position in cloud FPGA-based hardware accelerations for signal processing and data analysis

RnD INTERESTS[edit]

  • Measurement systems for investigating wafers, discrete devices, electronic panels, or PCB.
Designing low-cost circuits for I-V monitoring and impedance measuring. 
Deploying sustainable soft-CPU based FPGA platforms for entire processes from development to mass-production by means of git repository and other cowork tools.
Partitioning HW submodules in a debug-friendly style in the developing phase.
Guiding impedance-controlled PCB manufacture (PCB stackup, plane-cutout and via-hole locations) for less cross-talk and reflection on the PCB traces.
Considering circuit protections such as ESD, signal/power isolations, chassis grounding, and thermal issues.
  • Algorithms in embedded systems
Prototyping FPGA system architecture based on a good knowledge of hardware interface in real-time applications.
Partitioning HW and SW portions for high-throughput vs reliable/tracible features.
Realizing numerically complex algorithms on embedded sampled data acquisition systems.
  • Data analysis in adaptive filtering
Analyzing and stabilizing adaptive least-square filters and real-time algorithms in a view of regularization.
Parallelizing least squares algorithms based on projection subspaces.

EDUCATION[edit]

Dissertation: Consistent Adaptive Algorithms using Noise Variance Estimation and Errors-in-Variables Modeling
Advisor: Prof. Sang Woo Kim
  • MS (1999) and BS (1997) in Electronic and Electrical Engineering, POSTECH
Master Thesis: Normalized Iterative Feedback Tuning with a Convex Criterion Function
Advisor: Prof. Jin S. Lee

EXPERIENCE[edit]

  • 2023 - : Research Fellow, New Tech Center, NPP, Seoul, South Korea.
- Connsulting some device synchorization with clock distribution circuits (CDC) among DAC, ADC and FPGA (2024).
- Developing the logic-based controller for generating RF patterns in a directional coupled sensor system (2024).
- Directed the build-up of FPGA-based systems for RF signal processing (2023).
  • 2020 - 2023: Principal Research Engineer, Test Module Team, TOP ENGINEERING, Seongnam, South Korea.
-Implemented Frequency counter, range 1kHz ~ 10MHz, in FPGA system; counting rising edges of pulses based on 100MHz clock, and compensating base time by reference clock (2023). 
-Improved FW performance to qualify better-timed ADC measure data in SMU boards. (2023)
-Built up FPGA logic design flow that can be verified with the MicroBlaze CPU firmware under Visual Studio Code environment. (2022)
-Architected SPI protocol and physical interface to access HW endpoints implemented in FPGA devices for measurement system with multiple slave boards. (2021)
  Note: SPI transfer rate 6.5Mbps is supported for the compatibilty with legacy mode. RS-422 interface is used.
-Designed FPGA system supporting USB/LAN/SPI command protocol for 16-channel, 2.4Msps 16-bit ADC application of DDR 48MHz LVDS interface. (2020)
  Note: MAX transfer rate = (48 MHz) * (16 bit/channel) * (2 DDR) * (16 channel) = 24.576 Gbps inside board with 4 quad ADC ICs.
-Deployed DSP slices in the FPGA application to implement DFT of Floating-point numbers for impedance calculation. (2020)
-Designed the low-price version of the FPGA module by removing unused memories and devices. (2020)
  • 2017 - 2019: Principal Research Engineer, Precedent Development Team, TOP CENTRAL R&D CENTER (a subsidiary of TOP ENGINEERING), Seongnam, South Korea.
-Prototyped FPGA-based pulse generation unit with 400Msps dual DAC, 16-bit SDR 400MHz LVDS interface, and LAN command protocol. (2019).
-Designed undersampling dual ADC system for phase information reconstruction under coherent sampling condition: up-to 15MHz signals with the sampling rate less than their Nyquist rates. (2019)
-Deployed FPGA-based measurement platform for conditioning analog signals and processing ADC data (15Msps, 18bit, DDR 105MHz 2-lane interface), based on USB 3.0 module XEM7310.(2018)
-Analyzed measurement bridge circuits of parametric measure units for automatic test equipment. (2017) 
-Designed pulse generation command protocol based on SCPI for pulse generation unit. (2017)

-Revised FPGA (Altera Stratix-IV device) system with PCIe bus and SPI external peripherals for mass-production inspection of MLCC.
-Improved Mobile Industry Processor Interface (MIPI) interface board ESD and EMI design (schematics and gerber data) for mass-production inspection of camera modules.(2015-2016)
-Profiled SCPI protocol and implement a TCPIP socket server in FPGA platform.(2013-2014)
-Synchronized the triggers of Acousto-optic modulator and laser source.(2011-2012)
-Prototyped a FPGA-based controller for laser drill machine.(2010)
-Joined the Equipment Automation Group.(2010)
  • 2007 - 2010: Senior Staff Engineer, SEMCO.
-Designed and prototyped a ISM-band radio localization system with GPS synchronized base-stations.(2009)
-Verified the PHY performance on Vertex-5 FPGA platform and c simulator as well.(2008)
-Designed and integrated the RTL modules of IEEE 802.11n PHY, supporting 2 spatial streams up to 300Mbps.(2007)

Faculty Sponsor: Prof. Gene H. Golub
-Investigated the application of singular value decomposition (SVD), total least squares (TLS) and secular equations.

Faculty sponsor: Prof. V. Balakrishnan
-Conducted a research on unbiased adaptive filtering.
  • 1999 – 2005: Research and Teaching Assistant, Intelligent System & Control lab., POSTECH
-Developed embedded system for DC Drive 3-Phase Power Monitor including circuit schematics and PCB layout.
-Programmed applications to detect voltage dips and excess currents on power lines, and to signal trips to circuit brakers.
-Set up the lab. of Intel MCS-51 Processor Application: DC Motor Speed Control.
  • 1997 – 1999: Research and Teaching Assistant, Robotics & Automation Lab., POSTECH
-Developed Network Interface Device for Programmable Logic Controller.
-Set up the lab. of Music Player and Stepper Motor Controller through PC parallel port and Intel 8086 Trainer Kit.

GRANTS[edit]

TALK[edit]

  • Linear Algebra / Optimization Seminar, Fall Quarter at Stanford University, Stanford, CA, December 7, 2005.
Least Squares Problems with Equality Constraints on Residuals: TLS, DLS and Partial Data Analysis using Secular Equations

PUBLICATIONS[edit]

Journal[edit]

  • [1] S. Jo and S. W. Kim, "Consistent normalized least mean square filtering with noisy data matrix," IEEE Trans. Signal Processing, vol. 53, no. 6, pp.2112-2123, Jun. 2005.
  • [2] S. Jo, S. W. Kim and Jin S. Lee, "Normalized iterative feedback tuning with time constraints," IEICE Trans. Fundamentals, vol. E84-A, no.2, pp.681-687, Feb. 2001.

Conference[edit]

  • [3] S. Jo, S. W. Kim and T. J. Park, "Equally constrained affine projection algorithm," in Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, vol. 1, pp. 955-959, Nov. 7-10, 2004.
  • [4] S. Jo and S. W. Kim, "Normalized feedback iterative tuning with modified feedback experiment," in Proc. American Control Conference, pp.612-617, 2001.
  • [5] S. Jo and S. W. Kim, "Normalized iterative feedback tuning with PD-type modified feedback experiment," in Proc. IEEE International Symposium on Industrial Electronics, pp.1192-1197, 2001.
  • [6] S. Jo, S. W. Kim, P. Park, J. S. Lee and T. J. Park, "Normalized iterative feedback tuning with blended control criteria," in Proc. IASTED International Conference on Control and Application, pp.198-204, 2000.

Patents[edit]

PROFESSIONAL ACTIVITIES[edit]

TECHNICAL SKILLS[edit]

Other Notes[edit]

  • COURSE WORK HIGHLIGHTS at POSTECH
System Identification Theory (EECE628); Estimation Theory (EECE627); Linear Optimal Control (EECE692H);
Introduction to Neural Networks (EECE553); Network Theory (EECE695M)
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